Read-only-memories (ROMs) as nonvolatile memories are capable of storing data, even with power turned off. In that the ROM is capable of reading the stored data but is incapable of changing it, the ROM is different from Random Access Memories (RAMs) capable of reading and writing data.
FIG. 1 illustrates a portion of a conventional ROM constructed in accordance with the invention. The illustrated ROM is disclosed in U.S. Pat. No. 5,835,421, entitled, “METHOD AND APPARATUS FOR REDUCING FAILURE DUE TO BIT LINE COUPLING AND REDUCING POWER COMSUMPTION IN A MEMORY”.
Referring to FIG. 1, the conventional ROM includes a bit cell array 100. The bit cell array 100 comprises a plurality of bit lines and word lines, which cross each other, and ROM bit cells located at cross points of the bit lines BL1, BL2, BL3 and BL4, and the word lines WL1, WL2, WL3 and W14. One ROM bit cell 10 is a basic unit of ROM for storing data. In addition, each of the bit lines BL1, BL2, BL and BL4 is connected to a multiplexer 20, and is selected by bit line select signals SEL1, SEL2, SEL3 and SEL4, which are inputted from a bit line select circuit 120. The ROM bit cells connected to the selected bit line become precharged by a precharge circuit 130 connected to the multiplexer 20, and the stored data is amplified through a sense amplifier 140 to be outputted. In order to prevent data error of the ROM bit cells 10 caused by a coupling effect between adjacent bit lines in precharging, the ROM includes an additional coupling prevention circuit such as the bit line select circuit 120.
In FIG. 1, the bit line select circuit 120 controls adjacent bit lines, e.g., BL1 and BL2, or BL3 and BL4, among bit lines BL1, BL2, BL3 and BL4 of the ROM so as not to be simultaneously selected employing the multiplexer 20 so that the coupling effect between adjacent bit lines can be prevented. The multiplexer 20 may be embodied employing NMOS (N-channel Metal Oxide Semiconductor) transistors.
Techniques for preventing the coupling effect between bit lines of the ROM are disclosed in U.S. Pat. No. 4,318,014, entitled, “SELECTIVE PRECHARGE CIRCUIT FOR READ-ONLY-MEMORY,” and U.S. Pat. No. 4,485,460, entitled, “ROM COUPLING REDUCING CIRCUITRY.”
While data error caused by the coupling effect between bit lines can be prevented in the above-mentioned patents, there is a disadvantage to the disclosed approaches that operational speed is reduced by selectively precharging bit lines using the NMOS multiplexer circuit.